Dynamic Workload Frequency Optimization

ABSTRACT

The embodiments described herein relate to dynamically detecting a frequency change condition for microprocessor performance. An instruction is received, and a frequency change condition associated with the received instruction is dynamically detected. A frequency modulation is performed in response to the dynamic detection. The frequency modulation includes selecting a second frequency for optimal instruction processing different from a first frequency, the first frequency being a default operating frequency of the microprocessor. Execution of the instruction is completed at the second frequency. Accordingly, incoming execution instructions are logically analyzed, and the processor frequency is selectively modified based on associated instruction conditions.

BACKGROUND

The embodiments described herein relate to processor design andarchitecture. More specifically, the embodiments relate to partitioningthe processor design for architecturally defined timing domains thatinfluence design cycle time and pipeline depth.

Timing design of a processor is static in that design cycle time isapplied uniformly across all circuits within a time domain based on anassumption of equal use. The design cycle time may be determined basedon an expected workload of the processor. In one embodiment, the designcycle time is determined based on a thermal design point (TDP) for theprocessor. As is known in the art, the TDP of a processor is a maximumamount of heat generated by the processor during typical operation.However, many workloads do not approach the TDP of the processor, and assuch these workloads may benefit from a faster cycle time.

One known solution for addressing the workload differentiation isaccomplished using a critical path monitor (CPM), which is a circuitthat measures an available timing margin in real-time, coupling outputfrom the circuit to a clock generation circuit to adjust clock frequencywithin cycles in response to an excess or inadequate timing margin. TheCPM periodically adjusts a processor voltage or frequency. However, theCPM continues to employ a uniform design cycle.

SUMMARY

A microprocessor, a method, and a computer program product are providedto support dynamic optimization of microprocessor performance.

According to one aspect, a microprocessor is provided having componentsconfigured to support dynamic optimization of performance. Themicroprocessor includes an architecture with a time domain partition.More specifically, the architecture has first and second circuits, eachin communication with a block. The first circuit is configured tooperate at a first frequency, and the second circuit is configured tooperate at a second frequency, with the second frequency being differentfrom the first frequency. The first frequency is a default operatingfrequency. The microprocessor further includes an instruction processingunit that functions to receive an instruction, and dynamically detect afrequency change condition associated with the instruction. In addition,the microprocessor further includes a frequency modulation unit incommunication with the control unit. The frequency modulation unitperforms a frequency modulation in response to the dynamic detection.More specifically, the frequency modulation unit selects the frequencyfor optimal instruction processing. An instruction execution unit isprovided in communication with the instruction processing unit andfunctions to complete execution of the instruction at the secondfrequency.

According to another aspect, a method is provided for supporting dynamicoptimization of microprocessor performance. An instruction is received,and a frequency change condition associated with the instruction isdynamically detected. A frequency modulation is performed in response tothe dynamic detection. The frequency modulation includes selecting asecond frequency for optimal instruction processing, with the secondfrequency being different from the first or default frequency. In oneembodiment, the first frequency is referred to as the default operatingfrequency. Execution of the instruction is completed at the secondfrequency.

According to yet another aspect, a computer program product is providedto support dynamic optimization of microprocessor performance. Thecomputer program product includes a computer readable storage devicehaving computer readable program code embodied therewith. The programcode is executable by a processor to receive an instruction, anddynamically detect a frequency change condition associated with theinstruction. A frequency modulation is performed in response to thedynamic detection, including selecting a second frequency for optimalinstruction processing different from a first frequency. The firstfrequency is a default operating frequency. Execution of the instructionis completed at the second frequency.

These and other features and advantages will become apparent from thefollowing detailed description of the presently preferred embodiment(s),taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

The drawings reference herein forms a part of the specification.Features shown in the drawings are meant as illustrative of only someembodiments, and not of all embodiments unless otherwise explicitlyindicated.

FIG. 1 depicts a flow chart illustrating a process for dynamicallyoptimizing microprocessor performance, according to an embodiment.

FIG. 2 depicts a flow chart illustrating a process for modulating thefrequency of a processor with a removed staging latch, according to anembodiment.

FIG. 3 depicts a block diagram illustrating a microprocessor designed tosupport dynamic workload frequency optimization, according to anembodiment.

FIG. 4 depicts a block diagram illustrating a microprocessor designed tosupport dynamic workload frequency optimization, according to anembodiment.

FIG. 5 depicts a flow chart illustrating another embodiment formodulating the frequency of a processor, according to an embodiment.

FIG. 6 depicts a block diagram illustrating a multi-frequencymicroprocessor design, according to an embodiment.

DETAILED DESCRIPTION

It will be readily understood that the components of the presentembodiment(s), as generally described and illustrated in the Figuresherein, may be arranged and designed in a wide variety of differentconfigurations. Thus, the following detailed description of theembodiments of the apparatus, system, and method of the presentembodiment(s), as presented in the Figures, is not intended to limit thescope of the embodiment(s), as claimed, but is merely representative ofselected embodiments.

Reference throughout this specification to “a select embodiment,” “oneembodiment,” or “an embodiment” means that a particular feature,structure, or characteristic described in connection with the embodimentis included in at least one embodiment described herein. Thus,appearances of the phrases “a select embodiment,” “in one embodiment,”or “in an embodiment” in various places throughout this specificationare not necessarily referring to the same embodiment.

The illustrated embodiments will be best understood by reference to thedrawings, wherein like parts are designated by like numerals throughout.The following description is intended only by way of example, and simplyillustrates certain selected embodiments of devices, systems, andprocesses that are consistent with the embodiment(s) as claimed herein.

As is known in the art, a central processing unit (CPU), such as amicroprocessor, is a device that is configured to execute computerprogram instructions retrieved from memory. Specifically, a CPU isconfigured to fetch or receive a program instruction corresponding to amemory address, decode the instruction, and execute the instruction. Theinstruction is executed by passing the decoded information of theinstruction as a sequence of control signals to other components of theCPU for performing the actions dictated by the instruction. In oneembodiment, if the instruction has an indirect address, or multileveladdress, the CPU is configured to read an effective address of theinstruction, and translate the effective address to a real address.

Circuitry within a conventional microprocessor is designed to operate atthe same frequency (i.e., same design timing requirement). All timingpaths within the microprocessor are held to a standard cycle time. Inone embodiment, the standard cycle time may be 500 ps. The detection offrequency change conditions is conventionally done by employing eitherexternal or internal critical path monitors associated with themicroprocessor, which subsequently change the operating frequency of themicroprocessor.

A selected group of circuits of a microprocessor may be specified tooperate at a lower frequency, allowing the selected group of circuits tobe designed with more power efficient logic or circuit styles andtopologies, or with higher threshold transistors to reduce leakagecurrents. Alternatively, and in on embodiment, the selected group ofcircuits can be set to operate on a lower voltage domain to reducepower. Because of the less aggressive timing requirements, the selectedgroup of circuits may be designed using fewer resources.

With reference to FIG. 1, a flowchart (100) is provided illustrating aprocess for dynamically optimizing microprocessor performance. A programinstruction is fetched or received (102). In one embodiment, fetchingthe instruction at step (102) includes reading a memory addressassociated with the fetched instruction. If the memory address is adirect address, then the address need not be translated to a realaddress. However, if the address is an indirect address, an addresstranslation is performed, such as an effective-to-real addresstranslation (ERAT) as shown and described in FIGS. 5 and 6.

The microprocessor is configured to operate at a default, referred toherein as a first frequency. For example, in one embodiment, all timingpaths may be held to the 500 ps standard. There may be instances whereoperation of the first frequency is not optimal for execution of theinstruction. For example, a particular workload may use a feature thatis considerably higher power or requires more time to complete than the500 ps cycle time. An analysis is performed on the instruction to decideif the frequency should be modified for optimal processing of theinstruction. The analysis determines if there is a frequency changecondition associated with the instruction (104). The determination atstep (104) includes dynamically detecting the frequency changecondition. In one embodiment, the dynamic detection at step (104)includes performing a logic analysis of the instruction. In anotherembodiment, the dynamic detection at step (104) includes performing alogic function of a control signal. Accordingly, the initial aspect ofthe dynamic optimization includes an assessment of the instruction.

A negative response to the determination at step (104) indicates thatthe instruction may be optimally processed at the default frequency,i.e. first frequency, and execution of the instruction is completed atthe first frequency (106). In other words, in this circumstance there isno frequency modulation for the associated instruction. However, apositive response to the determination at step (104) indicates that afrequency change condition has been detected. In one embodiment, thefrequency change condition is an ERAT miss requiring execution of theinstruction at a different frequency. Further details regarding theprocess for detecting an ERAT miss will be provided below in FIGS. 5 and6.

Following a positive response to the instruction assessment at step(104), a frequency modulation is performed (108). More specifically, thefrequency modulation at step (108) includes selecting a second frequencyfor optimal instruction processing, with the second frequency beingdifferent from the first frequency. For example, in one embodiment, thefirst frequency is a default frequency of 500 ps and the secondfrequency is 550 ps. Further details regarding the frequency modulationof step (108) will be discussed below with reference to FIGS. 2-4. Inone embodiment, a signal is created within the architecture of themicroprocessor to identify when the second frequency sub-domain is inuse. The signal would be calculated in advance and sent to the criticalpath monitor's (CPM's) control mechanism(s), where it can change thephase locked loop speed (PLL) in the microprocessor. In one embodiment,the CPM dynamically changes the PLL speed in the system to run at theslowest necessary frequency for any sub-domain in use at the time.Similarly, in one embodiment, the signal may be set to the PLL directly.

After the frequency modulation to the second frequency at step (108),execution of the instruction is completed at the second frequency (110).Upon completion of the workload, the CPM restores the PLL to the fullspeed of the normal timing domain (112). In one embodiment, the CPM maynot be in use and the signal would be communicated directly to the PLL.Accordingly, the process of FIG. 1 dynamically detects a conditionindicating that a fetched instruction should be processed at anon-default frequency, and completes execution of the instruction at thenon-default frequency.

Certain architectural features may benefit from reduced latency, even ata lower operating frequency. With reference to FIG. 2, a flowchart (200)is provided illustrating a process for modulating the frequency of aprocessor with a removed staging latch. An instruction that requiresdata propagation from a load store unit to an instruction execution unitis detected (202). As part of the instruction, the signal is sentwithout a staging latch to insert latency or pipeline depth to theexecuting instruction(s). A control is generated to lower the frequencyfrom the default frequency, e.g., 500 ps, to the second frequency, e.g.,550 ps, (204). Removal of the staging latch removes overhead. Followingstep (204), the clock generation and distribution receives the signaland changes the microprocessor frequency (206), allowing themicroprocessor subcomponents to execute instructions at the secondfrequency. Accordingly, as shown herein, a multi-frequency single clockdomain microprocessor design is provided.

With reference to FIG. 3, a block diagram (300) is provided illustratinga microprocessor (305) designed to support dynamic workload frequencyoptimization, according to an embodiment. As discussed above, aconventional microprocessor is associated with a standard cycle time ofa time-domain. However, a sub-domain of a microprocessor may be createdwithin the microprocessor architecture corresponding to a relaxed cycletime. For example, if the standard cycle time is 500 ps, the relaxedcycle time may be 550 ps (i.e., 10% relief). While in reality the timedomain will synchronously operate at a uniform cycle time across thewhole domain, the relaxation is created knowing that a control mechanismwill slow the cycle time accordingly while in use.

The microprocessor (305) includes a partitioned architecture (310). Thepartitioned architecture (310) is configured to create such atime-domain partition within the microprocessor (305). As shown, thepartitioned architecture (310) includes first circuitry (312) and secondcircuitry (314) each in communication with a set of sub-components. Thefirst circuitry (312) is in communication with a first set ofsub-components (322) configured to operate at the first frequency, andthe second circuitry (314) is in communication with a second set ofsub-components (324) configured to operate at the second frequency. Inone embodiment, the first frequency is a default operating frequency ofthe microprocessor (305). Similarly, in one embodiment, the secondfrequency is lower than the first frequency. Thus, the first and secondcircuitry (312) and (314) of the partitioned architecture (310) create atime domain partition within the microprocessor. Although only first andsecond circuitry (312) and (314) are shown in FIG. 3, it is to beunderstood and appreciated that additional circuitry may be provided inalternate embodiments, with each additional circuitry associated withrespective operating frequencies.

As shown, incoming instructions are received and analyzed at (350) todetermine frequency modulation of the signal and an associated timingcircuit and sub-components for processing the instructions. Based on theanalysis, in some circumstances, as shown and described in FIGS. 1 and2, the instruction will require or benefit from a frequency change(352). A frequency control mechanism (354) is activated for frequencymodulation, and a clock generation and electrical distribution unit(356) is employed to operate clock changes for the microprocessorfrequency. The frequency control mechanism (354) and clock generationand electrical distribution unit (356) may be comprised of any knowncomponents in accordance with the embodiments described herein. Forexample, a switch/multiplexer may be provided in communication with afirst reference clock associated with the first frequency and a secondreference clocked associated with the second frequency. The frequency iscontrolled by the switch/multiplexer by toggling between the first andsecond frequencies, as is known in the art. Other devices and/ortechniques may be used to perform the frequency modulation describedherein.

The clock changes communicate with all the microprocessor subcomponents.As such, based on the clock changes, a signal is communicated to thefirst or second set of sub-components (324) and (324), respectively, viathe first and second circuits (312) and (324), respectively. In oneembodiment, the select sub-components are configured to operate at a setfrequency or frequency range. By the clock generation (356) unitchanging the frequency, a signal is communicated to the circuitconfigured to complete execution of the instruction by utilizing theappropriate sub-components. Completion of instruction execution isdetected at (330).

Referring to FIG. 4, a block diagram (400) is provided illustrating amicroprocessor (405) designed to support dynamic workload frequencyoptimization, according to an embodiment. The micro-processor shown at(405) is a variant of the microprocessor shown in FIG. 3, with likenumbers representing like parts. As shown, the frequency controlmechanism (354) is replaced with a switch (460) to toggle between twofrequencies (462) and (464). Based on the frequency selection asdictated by the switch (460), the clock generation and electricaldistribution unit (456) is employed to operate clock changes for themicroprocessor frequency. In the example shown herein selection of thefirst frequency (462) will result in the clock distribution (456)initiating a signal to the first circuitry (412), and selection of thesecond frequency (464) will result in the clock distribution initiatinga signal to the second circuitry (414). Accordingly, the frequency iscontrolled by the switch/multiplexer by toggling between the first andsecond frequencies.

Referring to FIG. 5, a flow chart (500) is provided illustrating anotherembodiment for modulating the frequency of a processor. Certain circuitsin a microprocessor may be used more than others. Frequency modulationmay be tied to circuit categorization. In one embodiment, an instructioncategory or event may be assigned to specific circuits. Similarly, inone embodiment, address translation logic is designed to operate at alower frequency. In the majority of operation cycle, the addresstranslation logic is not used since most of the instruction loads getthe address translation using an address translation buffer or cache.The process shown herein as directed to an address translation miss. Aninstruction associated with an indirect memory address is fetched (502),and an ERAT unit is engaged to translate the indirect, e.g. virtual,addresses to real address (504). In response to detection of an addresstranslation miss by the ERAT unit (506), an associated ERAT miss signalis employed to modulate the processor to the second frequency (508),allowing microprocessor sub-components associated with the ERAT toexecute the instruction at the second frequency (510). After theinstruction associated with the translated address has executed, thefrequency is restored (512). Further details with respect to ERAT missdetection will be provided below in FIG. 6. An ERAT miss is one exampleof an event that may occur that would not be predicted or detected byprocessing the incoming instruction type and may trigger the need toactivate or use the second frequency domain. In one embodiment, theevent may activate a circuit to execute the instructions at the secondfrequency. Accordingly, in this example, the frequency of themicrocontroller is modulated to translate an effective address of aprogram instruction to a real address in response to an ERAT miss.

With reference to FIG. 6, a block diagram (600) is provided illustratinga multi-frequency microprocessor design. As shown, the processor isprovided with L2 cache (612), and a load/store unit (614). The cache(612) is a memory bank, and the load/store unit (614) is a hardwareelement that loads data from memory or stores it back to memory fromhardware registers (not shown). With respect to instructions, theprocessor is shown herein with an instruction fetch and decode unit(620), an instruction sequence unit (622), and an instruction executionunit (624). The instruction fetch and decode unit (620) functions toreceive an instruction and to translate the received instruction forexecution. As described herein, the translation of the instruction mayrelate to an associated circuit selection and execution frequency. Theinstruction sequence unit (624) pertains to placing the receivedinstructions in an order. In one embodiment, the sequence may be linear.Similarly, in one embodiment, the order may be interrupted with a branchinstruction, which may change the order of execution. The instructionexecution unit (624) functions to manage execution of the orderedinstructions.

As further shown, the processor is configured with an effective toreal-address translation (ERAT) unit (630). As shown and describedabove, one or more circuits in the process may be event driven or via aninstruction category. In such cases, limited portions of themicroprocessor are set up to detect events. As shown, herein, the ERATunit (630) is an example of processor hardware that translated indirect,e.g. virtual, addresses to real address. A signal is generated by theERAT unit (630) to hardware modulating the processor frequency inresponse to an ERAT miss. As an instruction is received or fetched bythe processor (610), the ERAT unit (630) may detect that an address ofthe received instruction requires translation, and the address of theinstruction is translated (632). In one embodiment, an associated ERATmiss is detected (634), and a control signal is generated (636) tomodulate the frequency for the associated instruction to translate theaddress at the modulated frequency. The control signal is communicatedto the lock distribution unit (640), which makes changes to themicroprocessor frequency, as shown and described in FIGS. 3 and 4.

The dynamic optimization feature of the microprocessor as shown anddescribed in the flow charts and block diagrams of FIGS. 1-6 allows foroperation at the highest performance possible based on constraints orfeatures of the microprocessor workload. One advantage of the frequencymodulation is that the fastest speed possible for workload execution isnot limited by a “weakest link” in a chain corresponding to certainworkloads. Another advantage is that new workloads could have hardwaresupport adopted into the microprocessor design while being lessdisruptive to the overall design process.

The described features, structures, or characteristics may be combinedin any suitable manner in one or more embodiments. In the followingdescription, numerous specific details are provided, such as examples ofagents, to provide a thorough understanding of the embodiment(s). Oneskilled in the relevant art will recognize, however, that theembodiment(s) can be practiced without one or more of the specificdetails, or with other methods, components, materials, etc. In otherinstances, well-known structures, materials, or operations are not shownor described in detail to avoid obscuring aspects.

The present embodiment(s) may be a system, a method, and/or a computerprogram product. The computer program product may include a computerreadable storage medium (or media) having computer readable programinstructions thereon for causing a processor to carry out aspects of thepresent embodiment(s).

The computer readable storage medium can be a tangible device that canretain and store instructions for use by an instruction executiondevice. The computer readable storage medium may be, for example, but isnot limited to, an electronic storage device, a magnetic storage device,an optical storage device, an electromagnetic storage device, asemiconductor storage device, or any suitable combination of theforegoing. A non-exhaustive list of more specific examples of thecomputer readable storage medium includes the following: a portablecomputer diskette, a hard disk, a random access memory (RAM), aread-only memory (ROM), an erasable programmable read-only memory (EPROMor Flash memory), a static random access memory (SRAM), a portablecompact disc read-only memory (CD-ROM), a digital versatile disk (DVD),a memory stick, a floppy disk, a mechanically encoded device such aspunch-cards or raised structures in a groove having instructionsrecorded thereon, and any suitable combination of the foregoing. Acomputer readable storage medium, as used herein, is not to be construedas being transitory signals per se, such as radio waves or other freelypropagating electromagnetic waves, electromagnetic waves propagatingthrough a waveguide or other transmission media (e.g., light pulsespassing through a fiber-optic cable), or electrical signals transmittedthrough a wire.

Computer readable program instructions described herein can bedownloaded to respective computing/processing devices from a computerreadable storage medium or to an external computer or external storagedevice via a network, for example, the Internet, a local area network, awide area network and/or a wireless network. The network may comprisecopper transmission cables, optical transmission fibers, wirelesstransmission, routers, firewalls, switches, gateway computers and/oredge servers. A network adapter card or network interface in eachcomputing/processing device receives computer readable programinstructions from the network and forwards the computer readable programinstructions for storage in a computer readable storage medium withinthe respective computing/processing device.

Computer readable program instructions for carrying out operations ofthe present embodiment(s) may be assembler instructions,instruction-set-architecture (ISA) instructions, machine instructions,machine dependent instructions, microcode, firmware instructions,state-setting data, or either source code or object code written in anycombination of one or more programming languages, including an objectoriented programming language such as Smalltalk, C++ or the like, andconventional procedural programming languages, such as the “C”programming language or similar programming languages. The computerreadable program instructions may execute entirely on the user'scomputer, partly on the user's computer, as a stand-alone softwarepackage, partly on the user's computer and partly on a remote computeror entirely on the remote computer or server. In the latter scenario,the remote computer may be connected to the user's computer through anytype of network, including a local area network (LAN) or a wide areanetwork (WAN), or the connection may be made to an external computer(for example, through the Internet using an Internet Service Provider).In some embodiments, electronic circuitry including, for example,programmable logic circuitry, field-programmable gate arrays (FPGA), orprogrammable logic arrays (PLA) may execute the computer readableprogram instructions by utilizing state information of the computerreadable program instructions to personalize the electronic circuitry,in order to perform aspects of the present embodiment(s).

Aspects of the present embodiment(s) are described herein with referenceto flowchart illustrations and/or block diagrams of methods, apparatus(systems), and computer program products. It will be understood thateach block of the flowchart illustrations and/or block diagrams, andcombinations of blocks in the flowchart illustrations and/or blockdiagrams, can be implemented by computer readable program instructions.

These computer readable program instructions may be provided to aprocessor of a general purpose computer, special purpose computer, orother programmable data processing apparatus to produce a machine, suchthat the instructions, which execute via the processor of the computeror other programmable data processing apparatus, create means forimplementing the functions/acts specified in the flowchart and/or blockdiagram block or blocks. These computer readable program instructionsmay also be stored in a computer readable storage medium that can directa computer, a programmable data processing apparatus, and/or otherdevices to function in a particular manner, such that the computerreadable storage medium having instructions stored therein comprises anarticle of manufacture including instructions which implement aspects ofthe function/act specified in the flowchart and/or block diagram blockor blocks.

The computer readable program instructions may also be loaded onto acomputer, other programmable data processing apparatus, or other deviceto cause a series of operational steps to be performed on the computer,other programmable apparatus or other device to produce a computerimplemented process, such that the instructions which execute on thecomputer, other programmable apparatus, or other device implement thefunctions/acts specified in the flowchart and/or block diagram block orblocks.

The flowchart and block diagrams in the Figures illustrate thearchitecture, functionality, and operation of possible implementationsof systems, methods, and computer program products according to thevarious embodiments. In this regard, each block in the flowchart orblock diagrams may represent a module, segment, or portion ofinstructions, which comprises one or more executable instructions forimplementing the specified logical function(s). In some alternativeimplementations, the functions noted in the block may occur out of theorder noted in the figures. For example, two blocks shown in successionmay, in fact, be executed substantially concurrently, or the blocks maysometimes be executed in the reverse order, depending upon thefunctionality involved. It will also be noted that each block of theblock diagrams and/or flowchart illustration, and combinations of blocksin the block diagrams and/or flowchart illustration, can be implementedby special purpose hardware-based systems that perform the specifiedfunctions or acts or carry out combinations of special purpose hardwareand computer instructions.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting. As used herein, thesingular forms “a”, “an” and “the” are intended to include the pluralforms as well, unless the context clearly indicates otherwise. It willbe further understood that the terms “comprises” and/or “comprising,”when used in this specification, specify the presence of statedfeatures, integers, steps, operations, elements, and/or components, butdo not preclude the presence or addition of one or more other features,integers, steps, operations, elements, components, and/or groupsthereof.

The corresponding structures, materials, acts, and equivalents of allmeans or step plus function elements in the claims below are intended toinclude any structure, material, or act for performing the function incombination with other claimed elements as specifically claimed. Thedescription of the present embodiment(s) has been presented for purposesof illustration and description, but is not intended to be exhaustive orlimited to the embodiment(s) in the form disclosed. Many modificationsand variations will be apparent to those of ordinary skill in the artwithout departing from the scope and spirit of the embodiment(s). Theembodiment was chosen and described in order to best explain theprinciples and the practical application, and to enable others ofordinary skill in the art to understand the embodiment(s) for variousembodiments with various modifications as are suited to the particularuse contemplated.

It will be appreciated that, although specific embodiments have beendescribed herein for purposes of illustration, various modifications maybe made without departing from the spirit and scope of the invention.Accordingly, the scope of protection of this invention is limited onlyby the following claims and their equivalents.

We claim:
 1. A microprocessor comprising: an architecture configured tocreate a time domain partition, the architecture comprising at leastfirst and second circuitry each in communication with a clock, whereinthe first circuitry is configured to operate at a first frequency, thesecond circuitry is configured to operate at a second frequencydifferent from the first frequency, and wherein the first frequency is adefault operating frequency; an instruction processing unit incommunication with the architecture the instruction processing unit toreceive an instruction, and dynamically detect a frequency changecondition associated with the instruction; a frequency modulation unitin communication with the instruction processing unit, the frequencymodulation unit to perform a frequency modulation in response to thedynamic detection, including the frequency modulation unit to select thesecond frequency for optimal instruction processing; and an instructionexecution unit in communication with the instruction processing unit,the instruction execution unit to complete execution of the instructionat the second frequency.
 2. The microprocessor of claim 1, furthercomprising the instruction processing unit to activate a circuit inresponse to detection of an event, the activated circuit to execute anassociated instruction at the second frequency.
 3. The microprocessor ofclaim 1, wherein the dynamic detection of the frequency change conditioncomprises the instruction processing unit to perform a logic analysis ofthe received instruction
 4. The microprocessor of claim 1, wherein thedynamic detection of the frequency change condition comprises theinstruction processing unit to perform a logic function on a controlsignal.
 5. The microprocessor of claim 1, wherein the frequencymodulation unit comprises a first reference clock associated with thefirst frequency, a second reference clock associated with the secondfrequency, and a switch in communication with the first and secondreference clocks.
 6. The microprocessor of claim 5, wherein performingthe frequency modulation comprises the switch to toggle between thefirst and second frequencies.
 7. The microprocessor of claim 1, whereinthe frequency modulation unit comprises a phase locked loop, and whereinperforming the frequency modulation comprises the phase locked loop tooutput the second frequency.
 8. The microprocessor of claim 1, furthercomprising the frequency modulation unit to restore operation to thefirst frequency in response to the execution of the instruction.
 9. Amethod comprising: receiving an instruction; dynamically detecting afrequency change condition associated with the received instruction;performing a frequency modulation in response to the dynamic detection,including selecting a second frequency for optimal instructionprocessing different from a first frequency, wherein the first frequencyis a default operating frequency; and completing execution of theinstruction at the second frequency.
 10. The method of claim 9, furthercomprising activating a circuit in response to detecting an event, theactivated circuit to execute an associated instruction at the secondfrequency.
 11. The method of claim 9, wherein the dynamic detection ofthe frequency change condition comprises performing a logic analysis ofthe received instruction
 12. The method of claim 9, wherein the dynamicdetection of the frequency change condition comprises performing a logicfunction on a control signal.
 13. The method of claim 9, whereinperforming the frequency modulation comprises a switch toggling betweenthe first and second frequencies, wherein the switch is in communicationwith a first reference clock associated with the first frequency and asecond reference clock associated with the second frequency.
 14. Themethod of claim 9, wherein performing the frequency modulation comprisesa phase locked loop outputting the second frequency.
 15. The method ofclaim 9, further comprising restoring operation to the first frequencyin response to the execution of the instruction.
 16. A computer programproduct comprising a computer readable storage device having programcode embodied therewith, the program code executable by a processingunit to: receive an instruction; dynamically detect a frequency changecondition associated with the received instruction; perform a frequencymodulation in response to the dynamic detection, including selecting asecond frequency for optimal instruction processing different from afirst frequency, wherein the first frequency is a default operatingfrequency; and complete execution of the instruction at the secondfrequency.
 17. The computer program product of claim 16, furthercomprising program code to activate a circuit in response to detectingan event, the activated circuit to execute an associated instruction atthe second frequency.
 18. The computer program product of claim 16,wherein the dynamic detection of the frequency change conditioncomprises program code to perform a logic analysis of the receivedinstruction
 19. The computer program product of claim 16, wherein thedynamic detection of the frequency change condition comprises programcode to perform a logic function on a control signal.
 20. The computerprogram product of claim 16, further comprising program code to restoreoperation to the first frequency in response to the execution of theinstruction.